Core Foundation Track

1: Digital Design & RTL Fundamentals

“Before you verify chips, you need to understand how they work.”

Topics Covered:

• Number systems, Boolean algebra, Karnaugh maps

• Combinational and Sequential Logic (Mux, Decoder, FFs, FSMs)

• Synchronous vs. Asynchronous design

• Timing diagrams and setup/hold concepts

• RTL coding using Verilog

• Simulation and waveform debugging

Mini Projects:

• 4-bit ALU Design + Verification

• FSM-based traffic light controller

• UART TX/RX architecture exploration

Hands-on Outcomes:

• Write synthesizable Verilog RTL

• Build and simulate simple designs in tools like ModelSim/Xrun

• Create waveform snapshots and debug functional mismatches

Review & Evaluation:

• Quiz on design principles and Verilog syntax

• Code review session with instructor

• Oral viva on FSM and state transitions

2: SystemVerilog Essentials + Testbench Development

“From hardware coding to verification thinking.”

Topics Covered:

• SystemVerilog data types: logic, bit, int, arrays

• Procedural blocks: always_ff, always_comb, initial

• Tasks vs. Functions

• Introduction to Object-Oriented Programming

• Interfaces, Modports, Clocking Blocks

• Basic functional coverage and constraints

Mini Projects:

• Packet structure generation with randomization

• Write task-based TB for ALU and UART

• Use of interfaces in TB abstraction

Hands-on Outcomes:

• Understand SV syntax and advanced constructs

• Write basic testbenches using SV

• Use random stimulus generation and monitor behavior

Review & Evaluation:

• Assignment: TB for counter and ALU with stimulus

• Hands-on test on queues, arrays, and OOP

• Peer review of randomized packet TB

3: UVM Introduction & Mini Verification Project

“Step into the world of scalable and reusable verification.”

Topics Covered:

• UVM architecture: sequence, driver, monitor, scoreboard

• Factory and Configuration DB

• Transaction modeling (TLM1)

• Testcases and UVM Phases

• Coverage models integration

• Report logging and simulation control

Mini Project:

• UVM testbench for APB-SRAM IP

• Write sequences for read/write transactions

• Implement basic scoreboard to compare expected vs actual

• Add coverage collection and report summaries

Hands-on Outcomes:

• Understand how UVM testbenches are structured

• Write basic UVM components and sequences

• Debug UVM logs and simulate with reports

Review & Evaluation:

• Functional test run with waveform proof

• Checklist-based code review

• Final viva covering UVM flow and coverage
  

  Silicon ProTrack
  
  SoC-Level Verification Mastery

“From integrating 10+ IPs to handling interrupts, resets, boot flows, and multi-core activity—learn what it means to verify a real SoC.”

Topics Covered:

• SoC architecture exploration (bus interconnects, memory maps, register planning)

• Integration verification (DMA, UART, SPI, AES, SHA, etc.)

• Multi-mode test planning: boot-time, functional, corner-case

• Reset sequencing, watchdog & clock-domain testing

• UVM integration at SoC level with multiple agents

• C-to-SV handshake, top-level memory decoding & access

Hands-on Projects:

• Build an SoC-level testbench with 3+ agents

• Integrate and test RAL model for full memory-mapped IPs

• Boot from SRAM/Flash and verify basic functionality

• Develop SoC interrupt tests using C + UVM coordination

2. C-Based Flow for HW/SW Co-Verification

“You don’t just write UVM tests—you bring up the SoC using embedded C and track it all the way from reset to register bring-up.”

Topics Covered:

• Bare-metal C test development for embedded SoC

• Reset vector configuration and memory map alignment

• SV DPI-C Interface: calling C functions from SV and vice versa

• Test harness creation to monitor system behavior

• Debugging boot failures and invalid reads/writes

• Testcase control via software flags and shared variables

Hands-on Projects:

• C-based memory and peripheral access tests

• Debug SoC integration by matching expected vs. actual data via logs

• Use DPI to create reference model checks from C

3. Formal Verification & Connectivity Checking

“Not everything needs to be simulated—some things must be proven.”

Topics Covered:

• Assertions using SVA: writing, binding, layering

• Formal tool flow (Synopsys VC Formal / Cadence Jasper)

• Protocol checkers for APB, AHB, AXI

• Connectivity checks (example: DMA source-to-target)

• Assumptions, constraints, vacuity and cover properties

• Integrating formal with simulation coverage

Hands-on Projects:

• Formal sign-off for bus protocol

• Prove connectivity of DMA/bridge/IP structures

• Debug false passes/failures and add assumptions

• Run assertion-based regression and generate proof coverage

4. AMS Verification using RNM & Co-Simulation

“When analog meets digital—bring both into your simulation universe.”

Topics Covered:

• Introduction to Real Number Modeling (RNM)

• Behavioral modeling of analog components: ADC, DAC, PLL, LDO

• Digital-analog interface modeling (mixed-signal boundaries)

• Co-simulation flows: digital + SPICE or AMS simulators

• Functional verification of signal integrity and data conversion paths

• Power domain awareness and analog reset sequences

Hands-on Projects:

• Model a charge pump or comparator in RNM

• Simulate a mixed-signal loop: digital control + analog output

• Use waveform viewers to correlate analog and digital signal phases

• Debug meta-stability, noise, and resolution violations

5. RISC-V Processor & Subsystem Verification

“Know how to boot it, validate it, and trap bugs buried deep in execution logic.”

Topics Covered:

• Understanding RISC-V architecture and privilege levels

• Verifying instruction decode, interrupt control, pipeline behavior

• C test writing for instruction sequences

• UVM testbench for processor + memory + peripherals

• DPI-C interface to RISC-V reference model

• Coverage metrics: functional, branch, instruction

Hands-on Projects:

• Boot a RISC-V core and verify memory-mapped peripheral access

• Implement instruction test sequences and compare via reference model

• Debug misfiring interrupts and trap behavior

• Setup test flow for cache/no-cache configurations

6. GLS / PA-GLS and SDF-Aware Debugging

“When timing matters—simulate with precision.”

Topics Covered:

• Gate-level netlist and SDF annotation basics

• GLS setup in VCS/Xrun with delay back-annotation

• Signal integrity and glitch handling

• Setup & Hold violations, race conditions

• PA-GLS: Pre-Silicon Power-Aware simulation flows

• SAIF/FSDB-based power domain switching checks

Hands-on Projects:

• Run SDF GLS on synthesized netlist of SoC

• Debug setup/hold violations with waveform and timing reports

• Inject unknown states (X) and test recovery logic

• Run power domain off/on scenarios with PA assertions